Decimating memories typically include a series of decimation registers, e.g. delay stages, having outputs coupled to arithmetic logic units (ALUs). These registers shift input data from register to register in an in-line or series fashion. Calculations are performed on the various register outputs provided to the arithmetic logic units. Decimating memories are useful in many applications such as for digital filter products wherein the output data rate is slower than the input data rate. In such a filter product, decimation can be used to implement a longer filter with only a limited amount of architectural hardware being necessary.
Conventionally, decimation memories are implemented using a series of shift registers which propagate the input data stream through the registers. However, this implementation requires that every piece of data in each individual shift register be moved when the data is propagated through the series of shift registers. This has the disadvantage of requiring a tremendous amount of power to operate the decimating memory. Further, prior known decimating memories utilize a large number of lines from the memory to implement the filter product. These lines take up space that could otherwise be useful for other circuit components.
There is therefore needed a decimating memory which overcomes the disadvantages of the prior art and performs decimation functions in an economical manner.